If Statements and Case Statements in Verilog
In this post we talk about two of the most commonly used constructs in verilog - the if statement and the case statement.
We have seen in a previous post how use procedural blocks such as the always block to write verilog code which is executed sequentially .
We can also use a number of statements within procedural blocks which control the way that signals are assigned in our verilog designs. Collectively, these statements are known as sequential statements.
The case statement and the if statement are both examples of sequential statements in verilog.
In the rest of this post, we talk about how both of these statements are used in verilog. We then consider a short example for both of these constructs to show how we use them in practise.
Verilog If Statement
The if statement is a conditional statement which uses boolean conditions to determine which blocks of verilog code to execute.
Whenever a condition evaluates as true, the code branch associated with that condition is executed.
This statement is similar to if statements used in other programming languages such as C.
The verilog code snippet below shows the basic syntax for the if statement.
We can exclude the else and else if branches from the statement if we don't need them.
In fact, we have already seen this in the post on always blocks where we used the posedge macro to detect the rising edge of a clock signal.
We can include as many else if branches as necessary to properly model the underlying circuit.
The if statement uses boolean conditions to determine which lines of code to execute.
In the snippet above, these expressions are given by <expression1> and <expression2>.
These expressions are sequentially evaluated and the code associated with the expression is executed if it evaluates to true.
Only one branch of an if statement will ever execute. This is normally the first expression which evaluates as true.
The only exception to this occurs when none of the expressions are true. In this instance, the code in the else branch will execute.
When we omit the else branch in our if statement code then none of the branches will execute in this case.
The code associated with each branch can include any valid verilog code, including further if statements. This approach is known as nested if statements.
When using this type of code in verilog, we should take care to limit the number of nested statements as it can lead to difficulties in meeting timing.
- If Statement Example
We have already seen a practical example of the if statement when modelling flip flops in the post on the verilog always block .
To demonstrate this construct more thoroughly, let's consider an example of a clocked multiplexor.
In this instance, we will use an asynchronously resettable D type flip flop to register the output of a multiplexor .
The circuit diagram below shows the circuit which we will use in this example.
The code snippet below shows how we implement this using a single always block and an if statement.
In this example, we use the first if statement to set the output of the flip flop to 0b whenever reset is active.
When the reset is not active, then the always block has been triggered by the rising edge of the clock. We use the else branch of the first if statement to capture this condition.
We use a second if statement to model the behaviour of the multiplexor circuit. This is an example of a nested if statement in verilog.
When the addr signal is 0b, we assign the output of the flip flop to input a. We use the first branch of the nested if statement to capture this condition.
We then use the else branch of the nested if statement to capture the case when the addr signal is 1b.
It is also possible for us to use an else-if type statement here but the else statement is more succinct. The behaviour is the same in both cases as the signal can only ever be 0b or 1b in a real circuit.
Verilog Case Statement
We use the verilog case statement to select a block of code to execute based on the value of a given signal in our design.
When we write a case statement in verilog we specify an input signal to monitor and evaluate.
The value of this signal is then compared with the values specified in each branch of the case statement.
Once a match is found for the input signal value, the branch associated with that value will execute.
The verilog case statement performs the same function as the switch statement in the C programming language.
The code snippet below shows the general syntax for the case statement in verilog.
It is possible to exclude the default branch of the statement, although this is not advisable. If the default branch is excluded then all valid values of the <variable> must have it's own branch.
As with the if statement, the code associated with each branch can include any valid verilog code.
This includes further sequential statements, such as if or case statements. Again, we should try to limit the number of nested statements as it makes it easier to meet our timing requirements.
- Case Statement Example
To better demonstrate the way we use the case statement in verilog, let's consider a basic example.
For this example we will look at a simple four to one multiplexor circuit.
We frequently use the case statement to model large multiplexors in verilog as it produces more readable code than continuous assignment based implementations.
The code snippet below shows how we would implement this circuit using a case statement.
This example shows how simple it is to model a multiplexor using the case statement in verilog. In fact, the case statement provides the most intuitive way of modelling a multiplexor in verilog.
Although this example is quite straight forward, there are a few important points which we should consider in more detail.
The first thing to note in this example is that we use blocking assignment . The reason for this is that we are modelling combinational logic and non-blocking assignment normally leads to flip flops being placed in our design.
Another thing to note here is that we could remove the default keyword from this example. We would then explicitly list the value of addr required to output the value of d instead.
However, we have included the default keyword in this example to demonstrate how it should be used.
Which blocks do we use to write sequential statements in a verilog design?
Sequential statements can only be written within a procedural block such as an always block or initial block.
Which keywords can we exclude from the if statement when they are not required?
We can exclude the else and else if keywords if they are not needed.
How many branches of the if statement can be executed at one time?
A maximum of one branch in an if statement can execute at any time.
When can we exclude the default branch from the case statement?
We can exclude the default branch if all valid values of the input signal are explicitly listed.
Use a case statement to write the code for a six to one multiplexor.
Rewrite the six to one multiplexor from the last exercise so that it uses an if statement.
One comment on “If Statements and Case Statements in Verilog”
clearly explained with nice examples the style of the web page is also nice
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Verilog Conditional Statements
In Verilog, conditional statements are used to control the flow of execution based on certain conditions. There are several types of conditional statements in Verilog listed below.
The conditional operator allows you to assign a value to a variable based on a condition. If the condition is true, expression_1 is assigned to the variable. Otherwise, expression_2 is assigned.
Nested conditional operators
Conditional operators can be nested to any level but it can affect readability of code.
Here are some of the advantages of using conditional operators:
- Concise syntax : The conditional operator allows for a compact and concise representation of conditional assignments. It reduces the amount of code needed compared to using if-else statements or case statements.
- Readability : The conditional operator can enhance code readability, especially for simple conditional assignments. It clearly expresses the intent of assigning different values based on a condition in a single line.
And some disadvantages:
- Limited functionality : The conditional operator is primarily used for simple conditional assignments. It may not be suitable for complex conditions or multiple actions, as it can quickly become unreadable and difficult to maintain.
- Lack of flexibility : The conditional operator only allows for a binary choice based on the condition. It cannot handle multiple cases or multiple actions within a single line of code.
- Potential for reduced readability : While the conditional operator can enhance code readability for simple assignments, it can also make the code more difficult to understand if the condition and assigned values become complex.
The if-else statement allows you to perform different actions based on a condition.
If the condition evaluates to true, statement 1 is executed. Otherwise, statement 2 is executed.
Read more on Verilog if-else-if statements
The case statement is used when you have multiple conditions and want to perform different actions based on the value of a variable.
The expression is evaluated, and based on its value, the corresponding statement is executed. If none of the values match the expression, the statement under default is executed.
Read more on Verilog case statement