vhdl assign hex value to integer

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how to assign hex value to a variable

Thread starter j hemangini
Start date Aug 8, 2008
Aug 8, 2008

j hemangini

Member level 1.

assign hex value I want to creat a code in which there is variabe name let Data_Byte and want assign hex value 0x41, initially to this variable. Binary equivalent of this value is 01000001. According to my requirement after every 100 clock cycle only one bit should be on out pin (from bit no 0 to 7 one by one after every 100 clock cycle). So the main thing i want to ask is that how can i define this variable and how one bit can be transferred from this value. thank you.

llopacinski2

Newbie level 2.

assign hex values in vhdl If I understood: vhdl: signal Data_Byte : std_logic_vector( 7 downto 0) := x"41"; fifth bit: one_bit <= Data_Byte(5); --(data conversion can be needed) verilog: reg [7:0] Data_Byte = 8'h41; fifth_bit = Data_Byte[ 5];

Member level 2

vhdl assign hex You have to use "signal" not "variable" in order to put it on FPGA pin. first declare it.. signal Data_Byte : std_logic_vector(7 downto 0); hex value assignment.. Data_Byte <= x"BC"; For your problem first initialize.. Data_Byte <= x"01"; then every 100th clock edge, left rotate (by one bit) the whole register content.

vhdl assign value thanks for your reply. now i understood how to define hex value. But what instruction should i write for shift right. Thank you.

assigning hex values to #define Shift operators: Let A = “10010101” A sll 2 = “01010100” --shift left logical, filled with ‘0’ A srl 3 = “00010010” --shift right logical, filled with ‘0’ A sla 3 = “10101111” --shift left arithmetic, filled with right bit A sra 2 = “11100101” --shift right arithmetic, filled with left bit A rol 3 = “10101100” --rotate left by 3 A ror 5 = “10101100” --rotate right by 5 where sll, srl, sla, sra, rol, ror are vhdl keywords. For your application, you have to use: "A rol 1"

shift left logical for hexadecimal your reply was very helpful for me. I m very greatful to u. thank you.

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VHDL: Converting a Hexadecimal Value to a Standard Logic Vector

This example shows how to convert a hexadecimal value to a std_logic_vector . It is shown in both VHDL '87 (IEEE Std 1076-1987) and VHDL '93 (IEEE Std 1076-1993). For more information on using this example in your project, refer to the how to use VHDL examples section on the VHDL web page.

VHDL: Using hex values in constants

constants hex vhdl

I am a VHDL noob, trying to create a few constants and assign hex numbers to them, however I keep getting errors.

I want the constant FOO_CONST to be equal to 0x38

Like this…

constant FOO_CONST : integer := x"38";

Type integer does not match with a string literal

I've tried a few variants with no success.

I'd appreciate any help. Thanks!

Best Solution

You can specify a base for integers by using the format base#value# :

Python – Convert hex string to int in Python

Without the 0x prefix, you need to specify the base explicitly, otherwise there's no way to tell:

With the 0x prefix, Python can distinguish hex and decimal automatically.

(You must specify 0 as the base in order to invoke this prefix-guessing behavior; if you omit the second parameter int() will assume base-10.)

How to assign a hex or decimal value to a std_logic_vector of length 19 bits?

A bird in the hand may be worth two in the bush, but it sure makes it hard to type.

-- Rob Gaddi, Highland Technology Email address is currently out of order

> I write almost exclusively Verilog code,

> I want to say: > > flash_addr_i <= 128; >

> > I can't believe there's no way to do this in VHDL? >

Kevin Jennings

Jonathan Bromley

>I write almost exclusively Verilog code, but I inherited a >VHDL project and I need to make some changes to it. >I'm trying to make this human-readable, but I'm not >versed with VHDL, so I have no clue even what to look this up >under: > >This code works, but it is not very readable: > >signal flash_addr_i : std_logic_vector (18 downto 0) ; >. . . > elsif ((flash_addr_i < 128) and write_flag = '1') then > -- How can a human being make sense of of this? > -- and why is 128 OK for the comparison above and not > -- for the assignment below?

> flash_addr_i <= "0000000000010000000"; > end if; >. . . >I want to say: > > flash_addr_i <= 128; > >But then I get messages about flash_addr_i is not compatible with >with type of 128.

>and if I try a hex constant like: > > flash_addr_i <= x"00080"; > >I get bit width mis-match problems.

>How can I write the equivalent of the Verilog: > >flash_addr_i <= 19'd128; >or >flash_addr_i <= 19'h80;

The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.

> Assignment can be handled through > the TO_UNSIGNED function as: > > flash_addr_i <= TO_UNSIGNED(128, 19);

>> signal flash_addr_i : std_logic_vector (18 downto 0) ; >> . . .

So it seems fair to assume that the poor devil is saddled with old code that uses std_logic_unsigned instead of numeric_std. CONV_STD_LOGIC_VECTOR is what he needs.

[email protected]

The monitor is easily attached to an AHB interface.... http://bknpk.no-ip.biz/AHB_MON/ahb_mon_1.html

> I guess I'll use Jonathan's suggestion of adding 128

> to another constant vector. That works for XST, which > makes sense because everywhere in the code I see stuff > like: > > flash_addr_i <= flash_addr_i + 1; > > Adding an integer constant to a std_logic_vector.

> Unfortunately the project is also full of case statements > with binary strings for the case values, which makes it > hard to read, too. However I'll get to those when I find > out that they're broken...

> This should get me by until I convert the whole project > to Verilog. Usually that helps me to understand other > people's code anyway.

Not a good thing if the rest of your project team is using VHDL. Probably ought to invest in training instead. VHDL is quite simple once you get past the initial learning stuff.

> There is no project "team" at this company or in other words, > I am the team.

Examples of VHDL Conversions

Using both numeric_std and std_logic_arith package files.

Below are the most common conversions used in VHDL. The page is broken up into two sections. The first half of the page shows conversions using the Numeric_Std package file. The second half of the page shows conversions using the Std_Logic_Arith package file. It is good practice to use the Numeric_Std package as you should not use Std_Logic_Arith . Since many people still insist on using it, both examples are demonstrated below.

Note that many of the below examples use the ‘length VHDL attribute . This attribute makes your code more portable and versatile, so it should be used.

Example Conversions using Numeric Std

Integer to Signed
Integer to Std_Logic_Vector
Integer to Unsigned
Std_Logic_Vector To Integer
Std_Logic_Vector To Signed
Std_Logic_Vector To Unsigned
Signed to Integer
Signed to Std_Logic_Vector
Signed to Unsigned
Unsigned to Integer
Unsigned to Signed
Unsigned to Std_Logic_Vector

Example Conversions using Std_Logic_Arith

Convert from integer to signed using numeric_std.

The below example uses the to_signed conversion, which requires two input parameters. The first is the signal that you want to convert, the second is the length of the resulting vector.

Convert from Integer to Std_Logic_Vector using Numeric_Std

First you need to think about the range of values stored in your integer. Can your integer be positive and negative? If so, you will need to use the to_signed() conversion. If your integer is only positive, you will need to use the to_unsigned() conversion.

Both of these conversion functions require two input parameters. The first is the signal that you want to convert, the second is the length of the resulting vector.

Convert from Integer to Unsigned using Numeric_Std

The below example uses the to_unsigned conversion, which requires two input parameters. The first is the signal that you want to convert, the second is the length of the resulting vector.

Convert from Std_Logic_Vector to Integer using Numeric_Std

First you need to think about the data that is represented by your std_logic_vector. Is it signed data or is it unsigned data? Signed data means that your std_logic_vector can be a positive or negative number. Unsigned data means that your std_logic_vector is only a positive number. The example below uses the unsigned() typecast, but if your data can be negative you need to use the signed() typecast. Once you cast your input std_logic_vector as unsigned or signed, then you can convert it to integer as shown below:

Convert from Std_Logic_Vector to Signed using Numeric_Std

This is an easy conversion, all you need to do is cast the std_logic_vector as signed as shown below:

Convert from Std_Logic_Vector to Unsigned using Numeric_Std

This is an easy conversion, all you need to do is cast the std_logic_vector as unsigned as shown below:

Convert from Signed to Integer using Numeric_Std

This is an easy conversion, all you need to do is use the to_integer function call from numeric_std as shown below:

Convert from Signed to Std_Logic_Vector using Numeric_Std

This is an easy conversion, all you need to do is use the std_logic_vector cast as shown below:

Convert from Signed to Unsigned using Numeric_Std

This is an easy conversion, all you need to do is use the unsigned cast as shown below:

Convert from Unsigned to Integer using Numeric_Std

Convert from unsigned to signed using numeric_std.

This is an easy conversion, all you need to do is use the signed cast as shown below:

Convert from Unsigned to Std_Logic_Vector using Numeric_Std

Convert from integer to signed using std_logic_arith.

The below example uses the conv_signed conversion, which requires two input parameters. The first is the signal that you want to convert, the second is the length of the resulting vector.

Convert from Integer to Std_Logic_Vector using Std_Logic_Arith

The below example uses the conv_std_logic_vector conversion, which requires two input parameters. The first is the signal that you want to convert, the second is the length of the resulting vector.

One thing to note here is that if you input a negative number into this conversion, then your output std_logic_vector will be represented in 2’s complement signed notation.

Convert from Integer to Unsigned using Std_Logic_Arith

The below example uses the conv_unsigned conversion, which requires two input parameters. The first is the signal that you want to convert, the second is the length of the resulting vector.

Convert from Std_Logic_Vector to Integer using Std_Logic_Arith

First you need to think about the data that is represented by your std_logic_vector. Is it signed data or is it unsigned data? Signed data means that your std_logic_vector can be a positive or negative number. Unsigned data means that your std_logic_vector is only a positive number. The example below uses the unsigned() typecast, but if your data can be negative you need to use the signed() typecast. Once your input std_logic_vector is unsigned or signed, then you can convert it to integer as shown below:

Convert from Std_Logic_Vector to Signed using Std_Logic_Arith

Convert from std_logic_vector to unsigned using std_logic_arith, convert from signed to integer using std_logic_arith.

This is an easy conversion, all you need to do is use the conv_integer function call from std_logic_arith as shown below:

Convert from Signed to Std_Logic_Vector using Std_Logic_Arith

Convert from signed to unsigned using std_logic_arith, convert from unsigned to integer using std_logic_arith, convert from unsigned to signed using std_logic_arith, convert from unsigned to std_logic_vector using std_logic_arith.

This is an easy conversion, all you need to do is use the std_logic_vector typecast as shown below:

Learn Verilog

One Comment

This page is super useful!!

Hexadecimal representation

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VHDL: How can I truncate a hex constant to match a smaller vector?

Author Topic: VHDL: How can I truncate a hex constant to match a smaller vector? (Read 9174 times)

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Posts: 2051

Re: VHDL: How can I truncate a hex constant to match a smaller vector?

Mikeselectricstuff.

Posts: 13543

You could just make the signal 8 bits wide and tie the top bit low - it will get optimised out.

Posts: 2363

... but Quartus keeps giving me an error that the function isn't defined, even though I have the std_logic_arith package declared.

The Quartus II software contains support for VHDL 2008 with the following constructs defined in the IEEE Std 1076-2008 version of the IEEE Standard VHDL Language Reference Manual: ... Section 15.8—Enhanced Bit-string literals

Code: [Select] if (AsciiChar = 7x"0D") then ...

To make it more readable, you could create a subtype and a function

Use hex integer literals and to_unsigned to convert it to a vector of the required length, then std_logic_vector to convert it, if you don't use unsigned: Code: [Select] if AsciiChar = std_logic_vector(to_unsigned(16#0D#, 7)) then

But with a bit of luck Dongulus' tools support VHDL-2008, then it's problem solved in the exact same way as it is for verilog.

Quote from: mrflibble on March 17, 2014, 05:37:29 pm But with a bit of luck Dongulus' tools support VHDL-2008, then it's problem solved in the exact same way as it is for verilog.

Posts: 1461

Use verilog and abuse bit widths with impunity and at your own risk

Posts: 5550

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