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Task – Verilog Example

Write synthesizable and automatic tasks in verilog.

Tasks are sections of Verilog code that allow the Digital Designer to write more reusable, easier to read code. Tasks are very handy in testbench simulations because tasks can include timing delays . This is one of the main differences between tasks and functions , functions do not allow time delays .

Tasks should be utilized when the same operation is done over and over throughout Verilog code. Rather than rewriting code, one can just call the task. This reduces copy/paste errors in your code and allows quicker development time. It also makes the code much cleaner and easier to read. Yes, tasks can be synthesized!

Below is a list of rules for tasks:

  • Tasks can have any number of inputs and outputs
  • The order of inputs/outputs to a task dictates how it should be wired up when called
  • Tasks can have time delay (posedge, # delay, etc)
  • Tasks can call other tasks and functions
  • Tasks can drive global variables external to the task
  • Variables declared inside a task are local to that task
  • Tasks can use non-blocking and blocking assignments
  • Tasks can be automatic (see below for more detail)

Often tasks are created in the file they are used in. The example below demonstrates this. However tasks can also be included via the `include compile directive.

task_example.v:

The Modelsim simulation screenshot below shows the result of the operation of the task.

Modelsim results of Verilog task

Automatic Tasks

Tasks can be declared as automatic tasks as of Verilog 2001.

Automatic is a term borrowed from C which allows the task to be re-entrant. A re-entrant task is one in which the items declared within the task are allocated upon every individual call of the task, as opposed to being shared between all calls of the task. This could be a problem in a simulation environment if code is forked and calls the same task at the same time. Race conditions can develop.

In C, all variables are automatic by default. In order to make them not automatic, they must be declared as static . Verilog is the opposite with tasks. All tasks are static by default and should be declared automatic if they are called simultaneously. A good practice is to declare your tasks as automatic by default. The example below displays the difference between a re-entrant task and a regular task. The non-automatic task is likely not behaving the way the user intended!

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Using Tasks and Functions in Verilog

In this post we look at how we use tasks and functions in verilog. Collectively, these are known as subprograms and they allow us to write verilog code which is reusable .

As with most programming languages, we should try to make as much of our verilog code as possible reusable. This allows us to reduce development time for future projects as we can more easily port code from one design to another.

Whilst functions should be familiar to anyone with experience in other programming languages, tasks are less common in other languages.

There are two main differences between functions and tasks.

When we write a verilog function, it performs a calculation and returns a single value.

In contrast, a verilog task executes a number of sequential statements but doesn't return a value. Instead, the task can have an unlimited number of outputs

In addition to this, verilog functions execute immediately and can't contain time consuming constructs such as delays, posedge macros or wait statements

A verilog task , on the other hand, can contain time consuming constructs.

We will discuss both of these constructs in depth in the rest of this post. This includes giving examples of how we write and call functions and tasks in verilog.

Verilog Function

In verilog, a function is a subprogram which takes one or more input values, performs some calculation and returns an output value.

We use functions to implement small portions of code which we want to use in multiple places in our design.

By using a function instead of repeating the same code in several places, we make our code more maintainable .

We write the code for functions in the verilog module which we will use to call the function.

The code snippet below shows the general syntax for a function in verilog.

We must give every function a name, as denoted by the <name> field in the above example.

We can either declare the inputs inline with the function declaration or as part of the function body. The method we use to declare the input arguments has no affect on the performance of the function.

However, when we use inline declaration we can also omit the begin and end keywords if we want to.

We use the <arguments> field in the above example to declare the inputs to our function.

We use the <return_type> field to declare which verilog data type the function returns. If we exclude this part of the function declaration, then the function will return a 1 bit value by default.

When we return a value we do it by assigning a value to the name of the function. The code snippet below shows how we would simply return the input to a function. We can also simulate this example on EDA playground .

  • Rules for Using Functions in Verilog

Although functions are often fairly simple, there are a few basic rules which we must follow when we write a verilog function.

One of the most important rules of a function is that they can't contain any time consuming constructs such as delays, posedge macros or wait statements.

When we want to write a subprogram which consumes time we should use a verilog task instead.

As a result of this, we are also not able to call tasks from within a function. In contrast, we can call another function from within the body of a function.

As functions execute immediately, we can only use blocking assignment in our verilog functions.

When we write functions in verilog, we can declare and use local variables . This means that we can declare variables in the function which can't be accessed outside of the function it is declared in.

In addition to this, we can also access all global variables within a verilog function.

For example, if we declare a function within a module block then all of the variables declared in that module can be accessed and modified by the function.

The table below summarises the rules for using a function in verilog.

  • Verilog Function Example

To better demonstrate how to use a verilog function, let's consider a basic example.

For this example, we will write a function which takes 2 input arguments and returns the sum of them.

We use verilog integer types for the input arguments and the return types.

We must also make use of the verilog addition operator in order to calculate the sum of the inputs.

The code snippet below shows the implementation of this example function in verilog.

As we have previously discussed, there are two methods we can use to declare verilog functions and both of these are shown in the code below.

We can also simulate this example using EDA playground .

  • Calling a Function in Verilog

When we want to use a function in another part of our verilog design, we have to call it. The method we use to do this is similar to other programming languages.

When we call a function we pass parameters to the function in the same order as we declared them. This is known as positional association and it means that the order we declare our arguments in is very important.

The code snippet below shows how we would use positional association to call the addition example function .

In the example below, in_a would map to the a argument and in_b would map to b.

  • Automatic Functions in Verilog

We can also use the verilog automatic keyword to declare a function as reentrant .

However, the automatic keyword was introduced in the verilog 2001 standard meaning that we can't write reentrant functions when working with the verilog 1995 standard.

When we declare a function as reentrant, the variables and arguments within the function are dynamically allocated . In contrast, normal functions use static allocation for internal variables and arguments.

When we we write a normal function, all of the memory which is used to perform the processing of the function is allocated only once. This is process is known as static memory allocation in computer science.

As a result of this, our simulation software must execute the function in it's entirety before it can use the function again.

This also means that the memory the function uses is never deallocated . As a result of this, any values stored in this memory will maintain their value between calls to the function.

In contrast, functions which use the automatic keyword allocate memory whenever the function is called. The memory is then deallocated once the function has finished with it.

This process is known as automatic or dynamic memory allocation in computer science.

As a result of this, our simulation software can execute multiple instances of an automatic function.

We can use the automatic keyword to write recursive functions in verilog. This means we can create functions which call themselves to perform a calculation.

As an example, one common use case for recursive functions is calculating the factorial of a given number.

The code snippet below shows how we would use the automatic keyword to write a recursive function in verilog. We can also simulate this example using  EDA playground .

Verilog Task

We use verilog tasks to write small sections of code that we can reuse throughout our design.

Unlike functions, we can use time consuming constructs such as wait, posedge or delays (#) within a task. As a result of this, we can use both blocking and non-blocking assignment in verilog tasks.

Verilog tasks can also have any number of inputs and can also generate any number of outputs. This is in contrast to functions which can only return a single value.

These features mean tasks are best used to implement simple pieces of code which are repeated several times in our design. A good example of this would be driving the pins on a known interface, such as SPI or I2C .

We often write the code for tasks in the verilog module which will be used to call the task.

When we do this, we can also read or write any of the module's global variables inside of the task body.

We can also create global tasks which are shared by all modules in a given file. To do this we simply write the code for the task outside of the module declarations in the file.

The code snippet below shows the general syntax for a task in verilog.

As with functions, there are two ways in which we can declare a task but the performance of both approaches is the same.

We must give every task a name, as denoted by the <name> field above.

When we write tasks in verilog, we can declare and use local variables. This means that we can create variables in the task which can't be accessed outside of the task it is declared in.

In addition to this, we can also access all global variables within a verilog task.

Unlike verilog functions, we can call another task from within a task. We can also make calls to functions from within a task.

  • Verilog Task Example

Let's consider a simple example to better demonstrate how to write a verilog task.

For this example, we will write a basic task which can be used to generate a pulse. The length of the pulse can be specified when we call the task in our design.

In order to do this, we must declare a single time type input in our task.

We will generate the pulse on a global reg type signal so there is no need to declare any outputs for the task.

The verilog code below shows the implementation of this example using the two different styles of task. We can also simulate this example on EDA playground .

Although this example is quite simple, we can see here how we can use the verilog delay operator (#) in a task. If we attempted to write this code in a function, this would cause an error when we tried to compile it.

We can also see from this example that we don't return a value in the same way as we do with a function.

Instead, we simply assign values to any signals that we have access to either as inputs or as global variables.

We can include and drive as many signals as we want when we write a task in verilog.

  • Calling a Task in Verilog

As with functions, we must call a task when we want to use it in another part of our verilog design.

The method we use to do this is similar to the method used to call a function.

However, there is one important difference between calling tasks and functions in verilog.

When we call a task in verilog, we can't use it as part of an expression in the same way as we can a function.

We should instead think of task calls as being a short hand way of including a block of code into our design.

As with functions, we use positional association to pass paramaters to the task when we call it.

This simply means that we pass parameters to the task in the same order as we declared them when we wrote the task code.

The code snippet below shows how we would use positional association to call the pulse_generate task which we previously considered.

In this case, the pulse_length input is mapped to the pulse_time variable and the pulse output is mapped to the pulse_out variable.

  • Automatic Tasks in Verilog

We can also use the automatic keyword with verilog tasks in order to make them reentrant. Again, this keyword was introduced in the verilog 2001 standard meaning it can't be used with verilog 1995 compatible code.

As we talked about previously, using the automatic keyword means that our simulation tool uses dynamic memory allocation.

As with functions, tasks use static memory allocation by default which means that only one instance of a task can be run by the simulation software.

In contrast, tasks which use the automatic keyword allocate memory whenever the task is called. The memory is then freed once the task has finished with it.

Let's consider a basic example to show automatic tasks are used and how they differ from normals task.

For this example, we will use a simple task which increments the value of a local variable by a given amount.

We can then run this a number of times in a simulation tool to see how the local variable behaves using an automatic task and a normal task.

The code below shows how we write a static task to implement this example.

Running this code in the icarus verilog simulation tool results in the following output:

As we can see from this, the value of the local variable i is static and stored in a single memory location.

As a result of this, the value of i is persistent and it maintains it's value between calls to the task.

When we call the task we are incrementing the value which is already stored in the given memory location.

The code snippet below shows the same task except that this time we use the automatic keyword.

From this we can now see how the local variable i is dynamic and is created whenever the task is called. After it has been created, it is then assigned the value of 1.

When the task has finished running, the dynamically allocated memory is freed and the local variable no longer exists.

There are two main differences between tasks and functions, what are they?

A task can have ore than one output but a function can only have one. A function can not consume time but a task can.

What is the difference between an automatic function and a normal function in verilog?

Normal verilog functions use static memory allocation whereas automatic functions use dynamic memory allocation.

Write the code for a function which takes 3 integer inputs and returns the product of them.

Write the code for a task which returns the sum of 2 numbers. However, the result should be delayed by a fixed amount of time before it is returned. The task should take three inputs - one of time type which sets the delay time and the 2 integers that will be summed together. In addition, the task should have one output which is the result of the summation.

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task in Verilog

About the task keyword.

A task is a group of statements that would usually appear in an always block. If we need to repeat the same statements multiple times, it makes sense to define them as a task . Common examples include simple data format conversions, such as reversing the bit order in a vector. Say we have an 8-bit vector v . In some specifications, the Least Significant Bit (LSB) is on the “right”, i.e. v[0]. In other specifications, the LSB is on the “left”, i.e. v[7].

For some project, we may need to reverse the bit order of several vectors. This particularly occurs with filesystem interfaces and data communication channels. Do do this, we could use for loops, as in this code snippet:

This seems simple enough, but if we need to do this for many different signals, in multiple modules, it would make sense to group these lines into a simpler reusable statement. To accomplish this, we put the loop into a task like this:

Then to use the task , we reference it within an always block like this:

The task definition has to appear inside of the module. The automatic keyword is usually required; it instructs the simulator to allocate fresh memory every time the task is evaluated. The default non- automatic behavior has fewer applications and can create subtle simulation bugs.

So almost always your tasks should be automatic .

Assigned Tasks

Tasks in testbenches.

Tasks probably get the most use in testbenches. We’ll start with a simple example that simulates the reverse_bits_task shown above. In a text editor, open the file src/testbench.v . At the bottom of the testbench module, place the definition for reverse_bits_task . Find the always block that assigns q and w , and change it from for loops to task invocations. You should remove or comment out the declaration of idx since it is now defined within the task.

Type make to run the simulation. You should see several lines of output reporting a->q and b->w. Verify that the bits are correctly reversed in each case.

Tasks in Include Files

A task can be reused in a variety of different modules and testbenches. To facilitate this, Verilog has a ` include directive that imports lines from external files. You can use this to organize reverse_bits_task in its own file.

Move the reverse_bits_task definition into a file called inc/reverse_bits_task.v (remove or comment the task definition in testbench.v ). Then, in the testbench, add the include directive from inside the module:

Run the test again, you should get the same result.

Tasks in Modules

Next, remove or comment the ` include line in the testbench.v . Create a new module file named src/reverse_bits_module.v , to act as a “wrapper” for the task:

In the testbench, remove or comment the lines that reference the reverse_bits_task , and make an instance of reverse_bits_module . You will need to change q and w to wire types.

Implement reverse_bits_module

A task is synthesizable if it

  • Contains only synthesizeable statements, and
  • Is invoked within a synthesizeable module.

Examples of non-synthesizeable statements include:

  • Asynchronous time delays using #N syntax
  • System tasks like $display or $random
  • Complex math like division or trigonometric functions
  • Real-valued variables and operations

To be synthesizeable, a module needs inputs and outputs, and should be fully defined by synthesizeable statements; non-synthesizeable lines can exist for simulation purposes, but they are ignored during synthesis.

Fortunately for our task , a for loop is synthesizeable. With reverse_bits_module serving as a top module, we can synthesize and verify the design on the Basys3 board. Open reverse_bits.xdc and examine the constraints. Input vector a is mapped to switches 0–7, and input vector b is mapped to switches 8–15. Output vector q is mapped to LEDs 0–7, and w is mapped to 8–15. Also notice that there is no clock in this design.

Run make implement to build the design. Since there is no clock or other timing constraints in the design, the timing report is meaningless. The utilization report is more interesting. Open it and notice that there is no logic utilization – zero. The reverse_bits_task is implemented entirely in routing , i.e. switch configurations.

If successful, the build process should create reverse_bits.bit . Program the Basys3 board with this bitstream and verify that the left/right 8-bit groups are reversed. Verify and photograph the following cases:

  • Case 1: a= 00010011 , b= 01010101
  • Case 2: a= 11101100 , b= 01101001

Place photos of the two cases in your working directory, and name them case1 and case2 (with the appropriate graphics file extension).

Turn in Your Work

To complete this assignment, commit and push your results to the repository, and indicate on Canvas that it is complete:

Writing synthesizable Verilog

In the last year, I’ve started from scratch writing Verilog for hardware design. Coming from a software background where I was mainly using C/C++ and Python, it has been interesting to experience the contrasting philosophy and mindset associated with using a language to describe hardware circuits. Much of this is because Verilog provides little abstraction of hardware structures, and only through disciplined/idiomatic use, can efficient designs be implemented. A compounding issue is that complex hardware designs rely on a complex ecosystem of proprietary tooling.

As I see it, there are three aspects to writing synthesizable Verilog code: the particular features of the language to use, the style and idioms employed in using those features, and the tooling support for a design.

The language

A subset of Verilog is used for specifying synthesizable circuits. Verilog (which subsumed SystemVerilog as of the 2009 standardisation) is a unified language, serving distinct purposes of modern hardware design. These are:

  • behavioural
  • structural/register-transfer level ( RTL )
  • switch/transistor;
  • testbench-based verification;
  • specification of formal properties; and
  • specification of functional coverage.

The language provides specific features to serve each of these purposes. For hardware synthesis, each level of abstraction uses a different language subset, generally with fewer features at lower levels. Behavioural design uses the procedural features of Verilog (with little regard for the structural realisation of the circuit). RTL design specifies a circuit in terms of data flow through registers and logical operations. Gate- and switch-level design use only primitive operations. Typical modern hardware design uses a mix of register-transfer- and gate-level design.

It is interesting to note however that the specification of Verilog does not specify which features are synthesizable; that depends on the tooling used.

Coding style

Good coding style can help achieve better results in synthesis and simulation, as well as producing code that contains less errors and is understandable, reusable, and easily modifiable. Many of the observations in this note relate to coding style.

There is a variety of standard tooling that is used with Verilog, and indeed other hardware description languages (HDLs). This includes simulation, formal analysis/model checking, formal equivalence checking, coverage analysis, synthesis and physical layout, known collectively as electronic design automation tools ( EDA ). Since standard EDA tooling is developed and maintained as proprietary and closed-source software by companies like Cadence, Synopsis and Mentor, the tooling options are multiplied.

In contrast with the open-source software ecosystems of programming languages (for example), closed-source EDA tools do not benefit from the scale and momentum of open projects, in the way that conventional software languages do, with a one (or perhaps two) compilers and associated tooling such as debuggers and program analysers. Such a fragmented ecosystem inevitably has a larger variability in precisely how features of the Verilog language are implemented and which features are not supported, particularly since there is no standard synthesizable subset. Consequently, engineers using Verilog/HDLs with proprietary EDA tools do so conservatively, sticking to a lowest common denominator of the language features (within their chosen synthesizable subset), to ensure compatibility and good results.

This note records some interesting Verilog approaches and coding styles that I’ve observed that are used to interact well with the supporting tooling and to produce good synthesis results. I’ve written it as a note to myself, so it has the caveats that it assumes a familiarity with Verilog programming and that it’s not a comprehensive guide to Verilog programming practices; some of the references at the end will serve those purposes better.

My observations here are in the context of work on an implementation of a pipelined processor, as such different approaches may be taken with other types of electronic design. I also owe many of these insights to the guidance from my colleagues.

The remaining sections are as follows:

Combinatorial logic

Sequential logic, if statements, case statements, expressions, code structure, signal naming.

Use always_comb instead of always for combinatorial logic. The always_comb procedure allows tools to check that it does not contain any latched state and that no other processes assign to variables appearing on the left-hand side. (It’s worth checking the language reference manual ( LRM ) for details of of the other differences.) The use of an always_comb block is also a much clearer indication of a combinatorial block that the use of = as opposed to <= .

Always provide an initial value. A latch will be inferred if there exists a control-flow path in which a value of a signal is not set. Since always_comb specifically precludes the creation of latches, doing so will cause a warning or error in simulation or synthesis. For example, the following code implies a latch since there is no assignment to foo when the condition is not true.

Instead, always provide an initial value:

Avoid reading and writing a signal in an always_comb block. The sensitivity list includes variables and expressions but it excludes variables that occur on the right-hand side of assignments. According to these restrictions, a variable that is read and written in a block only causes the block to be reevaluated when the left-hand-side instance changes. However, this style can cause some tools to warn of a simulation-synthesis mismatch (presumably because they apply conservative rules from older versions of the language standard).

In the following code, the block is triggered only when the the right-hand-side foo changes, rather than entering a feedback loop where it shifts continuously:

To avoid reading and writing foo in the same block and possible warnings from tools, a new signal can be introduced:

Where possible extract logic into assign statements. Extract single assignments to a variable into a separate assign statement, where it is possible to do so. This approach uses the features of Verilog consistently, rather than using two mechanisms to achieve the same effect. This makes it clear that an always_comb is used to introduce sequentiality. Another opportunity to move logic into separate assign statements is with complex expressions, such as the Boolean value for a conditional statement. Doing this makes the control flow structure clearer, potentially provide opportunities for reuse, and provides a separate signal when inspecting the signals in a waveform viewer.

Avoid unnecessary sequentiality. It is easy to add statements to an always_comb to expand its behaviour, but this should only be done when there are true sequential dependencies between statements in the block. In general, parallelism should be exposed where ever possible. In the the following example, the sequentiality is not necessary since the output set_foo depends independently on the various conditions:

Clearly the sequencing of the conditions is not necessary, so the block could be transformed to separate the logic for each condition into separate parallel processes (extracting into assign statements as per the rule above) and explicitly combine them with the implied logical disjunction of the original block:

It is recommended by the author of Verilator to split up always blocks (combinatorial or sequential) so they contain as few statements as possible. This allows Verilator the most freedom to order the code to improve execution performance.

Drive one signal per block. With complex control flow statements, it is tempting to use a single always_comb block to drive multiple signals. In some circumstances, there may be good reasons to do this, such as when many output signals are used in a similar way, but in the general case, splitting each signal into a separate block makes it clear what logic involved in driving that signal, and as such, facilitates further simplification.

An additional reason to avoid driving multiple signals per always_comb block is that Verilator can infer a dependence between two signals, leading to false circular combinatorial loops. In these cases, it issues an UPOPTFLAT warning and cannot optimise the path, leading to reduced emulation performance. Generally, fixing warnings pertaning to unoptimisable constructs can improve Verilator’s simulation performance by up to a factor of two .

The above block could be split into two processes:

Use always_ff instead of always for sequential logic Similarly to always_comb , use of always_ff permits tools to check that the procedure only contains sequential logic behaviour (no timing controls and only one event control) that variables on the left-hand side are not written to by any other process, and makes clear the intent for sequential logic behaviour with non-blocking assignments, <= .

Avoid adding logic to non-blocking assignments. This is primarily a matter of taste, but having non-blocking assignments in always_ff blocks only from a logic signal name, rather than a logical expression, keeps the block simple and limits combinatorial logic to always_comb blocks and assign statements elsewhere in the module. Since synthesizable always_ff s are additionally restricted in that variables assigned to must have a reset condition of a constant value, maintaining this clarity aids the programmer. Having separate combinatorial blocks is also useful since it allows the logic signal driving a flip-flop as well as the registered value to be apparent in a waveform viewer, particularly when clock gates are used.

A typical pattern when implementing combinatorial logic and registers is to define the set and clear conditions in an always_comb and register the value in an accompanying always_ff , for example:

Use if qualifiers for single if and chained if-else statements for additional checking and guidance to synthesis:

  • unique to ensure exactly one condition is matched and to indicate the conditions can be checked in parallel.
  • unique0 to ensure one or no conditions match and to indicate the conditions can be checked in parallel.
  • priority to ensure one condition is matched and to indicate the conditions should be evaluated in sequence and only the body of the first matching condition is evaluated.

Note that:

  • The use of an else precludes violation reports for non-existing matches in unique and priority .
  • The default behaviour of a chained if-else block is priority but without any violation checks.

For example, when the conditions are mutually exclusive, so evaluation order is not important:

A violation warning is given in the above when no condition or multiple conditions are selected. Changing to unique0 will only check for multiple conditions being selected:

And adding an else will suppress violation warnings all together:

Use case qualifiers for additional checking and guidance to synthesis:

  • unique0 to ensure that one or no conditions are matched and to indicate the conditions can be checked in parallel.
  • priority to ensure one condition is matched and to indicate the conditions should be evaluated in sequence and only the body of the first matching case is evaluated.
  • The use of a default case precludes violation reports for non-existing matches in unique and priority .
  • The default behaviour of a case statement is that of priority , but without violation checks.

Use case (...) inside instead of casex or casez for matching don’t care bits. Since set-membership case (...) inside matches ? don’t care bits in the same way casez does, it should be used for clarity unless matching x s or z s is specifically required. For example:

Use case (1'b1) for one-hot conditions. For example:

As an aside, it is convenient to define a one-hot encoding in a union type with another struct to provide named access to each member. For example, status_q above could be redefined as:

Minimise the amount of logic inside a case statement. The rationale for this is similar to extracting logic from always_comb blocks into assign statements where possible: to make the control flow structure clearer to the designer and tooling, and to provide opportunities for reuse or further simplification. For example, avoid nesting case statements:

And instead extract a nested case into a separate process, providing a result signal to use in the parent case:

Although this example seems simple, the case -based logic driving a state machine can quickly become complicated.

Make operator associativity explicit. This is to avoid any ambiguity over the ordering of operators. In particular, always bracket the condition of a ternary/conditional expression ( ?: ), especially if you are nesting them, since they associate left to right, and all other arithmetic and logical operators associate right to left.

Make expression bit lengths explicit. Although the Verilog language specification provides rules for the extension of operands as inputs to binary operations and assignments, these are complicated and not always obvious. In particular, the extension is determined either by the operands or by the context of the expression. Since there may be inconsistencies between tools, particularly between simulation and synthesis, explicitly specifying expression bit widths avoids these issues and makes the intent obvious. For example, pad the result of a narrower expression for assignment:

Use an explicit type cast to specify the width of an intermediate expression (note that integer literals are interpreted as 32-bit integers):

Special care should be taken with sub expressions, since their result length is determined automatically by the width of the largest operand. For example, without an explicit type cast to a 17-bit result around a + b , the carry out bit would be lost:

Capture carry out bits (even if they are unused) so the left-hand-side assignment width matches the full width of the right hand side. Using a prefix like unused_ makes the process of signing off any related warnings with the downstream synthesis and physical build simpler:

Exceptions to this rule can be made for the common constants 0, 1 and -1 to be specified as integer literals, for example:

Use signed types for signed arithmetic, and avoid implementing signed arithmetic with manual sign extensions. Verilog uses the signedness of an expression to determine how to extend its width (as well as inferring signedness of parent expressions). Since the rules for sign determination is similar to expression size but not the same, making it explicit avoids errors. It also facilitates the use of optimised arithmetic implementations in synthesis, particularly with multipliers. The following example (adapted from this presentation ) shows how these rules can be confusing:

Note that an operation is only considered signed if all of the operands are signed, and that literal values can be specified as signed, for example: 2'sb11 is -1 in 2 bits.

Avoid splitting arithmetic between statements or modules. This facilitates optimisation during synthesis, for example, to choose or generate an optimised adder implementation for the given set of operands and carry ins/outs. Instead of:

All of the arithmetic contributing to sum can be written in a single expression:

Place parameters and variables at the top of their containing scope. Doing this gives and overview of the state and complexity of a block, particularly a module. Declarations of combinatorial and sequential nets should be separated into different sections for clarity. Note also that variables declared in unnamed scopes are not accessible via the design hierarchy and will not appear in wave viewers. To separate a module into sections without making signals inaccessible, a named scope can be introduced. The following example of a ripple-carry adder with registered outputs gives an idea of this style of structuring:

Use .* and .name() syntax to simplify port lists in module instantiations. This reduces the amount of boilerplate code and thus the scope for typing or copy-paste errors. .* also provides additional checks: it requires all nets be connected, it requires all nets to be the same size and it prevents implicit nets from being inferred. Named connections with .name() can be used to add specific exceptions. For example:

Avoid logic in module instantiations. By instantiating a module with a set of named signals, it is easier to inspect the port hookups and the widths of the signals for correctness.

A strict approach to naming should be taken to make it easier to understand and navigate a design:

To make clear their relationship to the structure of a module . Prefixes and suffices can denote, for example, whether a signal is an input or output, the pipeline stage it corresponds to and whether it is driven by logic or directly from a flip-flop. The exact naming convention will be tailored to a project, but here are some examples:

To allow simple sorting and searching in wave viewer . By using common prefixes for related signals, sorting will place them together. Similarly, common substrings are useful to filter a subset of signals over, for example to select a set of registers or similar signals different in pipeline stages.

To be flattened sensibly by downstream tools . It is typical for synthesis to flatten the hierarchical structure of a Verilog design. Consequently symbols names are derived from their place in the module hierarchy. A suitable naming scheme really only requires consistency across a design. As an example, a flip-flop clock pin might be named u_toplevel_u_submodule_p0_signal_q_reg_17_/CK corresponding to the register u_toplevel/u_submodule/p0_signal_q[17] .

Verilog is a large language with features supporting different purposes. It is used as a standard in hardware design but its specification does not define a synthesizable subset. Although there is a general consensus on which features can be used for synthesis, the fine details are determined by the particular EDA tooling flow used by a design team. Verilog is consequently used in a conservative way for specifying synthesizable designs. The rules and rationale given in this note outline some of the important aspects of a coding style for hardware design. There are many more details of Verilog’s features that are relevant; the references below are a good place to find out more.

References/further reading

  • IEEE Standard for SystemVerilog ( IEEE 1800-2012 and 1800-2017).
  • Stuart Sutherland and Don Mills, Standard gotchas subtleties in the Verilog and SystemVerilog standards that every engineer should know. SNUG 2006. ( PDF )
  • Stuart Sutherland, A Proposal for a Standard Synthesizable SystemVerilog Subset. DVCon 2006. ( PDF )
  • Stuart Sutherland and Don Mills, Synthesizing SystemVerilog: Busting the myth that SystemVerilog is only for verification, SNUG 2013. ( PDF ).
  • Stuart Sutherland and Don Mills, Can my synthesis compiler do that? What ASIC and FPGA synthesis compilers support in the SystemVerilog-2012 standard, DVCon 2014 ( PDF ).
  • SystemVerilog’s priority & unique - A Solution to Verilog’s “full_case” & “parallel_case” Evil Twins!, Clifford E. Cummings, SNUG 2005 ( PDF ).
  • Verilog HDL Coding, Semiconductor Reuse Standard, Freescale Semiconductor ( PDF ).
  • Complex Digital Systems, Synthesis, MIT OCW , 2005 (presentation slides, ( PDF ).

Please get in touch (mail @ this domain) with any comments, corrections or suggestions.

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SystemVerilog Arrays, Flexible and Synthesizable

In my last article on plain old Verilog Arrays , I discussed their very limited feature set. In comparison, SystemVerilog arrays have greatly expanded capabilities both for writing synthesizable RTL, and for writing non-synthesizable test benches. In this article, we’ll take a look at the synthesizable features of SystemVerilog Arrays we can use when writing design RTL.

Packed vs Unpacked SystemVerilog Arrays

Verilog had only one type of array. SystemVerilog arrays can be either packed or unpacked . Packed array refers to dimensions declared after the type and before the data identifier name. Unpacked array refers to the dimensions declared after the data identifier name.

Packed Arrays

A one-dimensional packed array is also called a vector. Packed array divides a vector into subfields, which can be accessed as array elements. A packed array is guaranteed to be represented as a contiguous set of bits in simulation and synthesis.

Packed arrays can be made of only the single bit data types ( bit , logic , reg ), enumerated types, and other packed arrays and packed structures. This also means you cannot have packed arrays of integer types with predefined widths (e.g. a packed array of byte ).

Unpacked arrays

Unpacked arrays can be made of any data type. Each fixed-size dimension is represented by an address range, such as [0:1023], or a single positive number to specify the size of a fixed-size unpacked array, such as [1024]. The notation [size] is equivalent to [0:size-1].

Indexing and Slicing SystemVerilog Arrays

Verilog arrays could only be accessed one element at a time. In SystemVerilog arrays, you can also select one or more contiguous elements of an array. This is called a slice . An array slice can only apply to one dimension; other dimensions must have single index values in an expression.

Multidimensional Arrays

Multidimensional arrays can be declared with both packed and unpacked dimensions. Creating a multidimensional packed array is analogous to slicing up a continuous vector into multiple dimensions.

When an array has multiple dimensions that can be logically grouped, it is a good idea to use typedef to define the multidimensional array in stages to enhance readability. But notice the order of the dimensions become a little confusing.

SystemVerilog Array Operations

SystemVerilog arrays support many more operations than their traditional Verilog counterparts.

+: and -: Notation

When accessing a range of indices (a slice ) of a SystemVerilog array, you can specify a variable slice by using the [start+:increment width] and [start-:decrement width] notations. They are simpler than needing to calculate the exact start and end indices when selecting a variable slice. The increment/decrement width must be a constant.

Assignments, Copying, and other Operations

SystemVerilog arrays support many more operations than Verilog arrays. The following operations can be performed on both packed and unpacked arrays.

Packed Array Assignment

A SystemVerilog packed array can be assigned at once like a multi-bit vector, or also as an individual element or slice, and more.

Unpacked Array Assignment

All or multiple elements of a SystemVerilog unpacked array can be assigned at once to a list of values. The list can contain values for individual array elements, or a default value for the entire array.

This article described the two new types of SystemVerilog arrays— packed and unpacked —as well as the many new features that can be used to manipulate SystemVerilog arrays. The features described in this article are all synthesizable, so you can safely use them in SystemVerilog based RTL designs to simplify coding. In the next part of the SystemVerilog arrays article, I will discuss more usages of SystemVerilog arrays that can make your SystemVerilog design code even more efficient. Stay tuned!

  • Synthesizing SystemVerilog: Busting the Myth that SystemVerilog is only for Verification
  • 1888-2012 IEEE Standard for SystemVerilog
  • SystemVerilog for Design Second Edition: A Guide to Using SystemVerilog for Hardware Design and Modeling

Sample Source Code

The accompany source code for this article is a toy example module and testbench that illustrates SystemVerilog array capabilities, including using an array as a port, assigning multi-dimensional arrays, and assigning slices of arrays. Download and run it to see how it works!

[lab_subscriber_download_form download_id=11].

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36 thoughts on “SystemVerilog Arrays, Flexible and Synthesizable”

Really nice article Jason. Makes for a great quick introduction and reference. I have personally found System Verilog arrays as one of the best ways to convert a Verilog user to System Verilog.

Chapter 5 and specifically Fig 5-5 in the System Verilog for Design book are the best: http://read.pudn.com/downloads166/sourcecode/math/758655/Springer%20-%20SystemVerilog%20for%20Design,%202nd%20Edition.pdf

I believe you have a mistake at the article. Regarding: busB = busA[7:6]; // select a 2-vector slice from busA busB = busA[6+:1]; // equivalent to busA[7:6]

but, busA[6+:1] is different from busA[7:6]! busA[6+:1] is actually busA[6:6] and: busA[6+:2] is busA[7:6]

Regards, Tomer

Hi Tomer. Yes you’re correct! I made a typo there, it’s fixed now. Thanks for spotting it!

I don’t see why we need packed/unpacked array for synthesis. FPGA is not limited with a fix size of memory like computer. The compiler should keep only what we need. Compiler will never allocate useless bits, it’s even opposite.

Same for packed and unpacked struct. What is the purpose if not only simulation speed?

Hi Alexis. If your question is why the packed versions are needed, with traditional synthesis tools you need packed arrays/structs/unions to tell the synthesis tool exactly how many bits and how you want to pack a datastructure. FPGA actually does have limited resources, and each additional (unnecessary) bit of a calculation takes up an additional lookup table. Similarly an extra bit in a calculation will require more gates in an ASIC. I wonder if part of the reason came from this desire for hardware engineers to have complete low level control of the synthesis result.

However, I think generally synthesis tools and Verilog/SystemVerilog rules are smart enough to figure out the minimum number of bits you want in a calculation. So you could argue since tools are so smart, why do we still need to specify the packing. I don’t have a good answer, but I think one day (maybe soon) you will be right and we won’t need to specify packed structures anymore.

I see, exactly since the synthesis tools removes the unused bits from the RTL. Then even if I set unpacked array, at the end, the RTL will be as if I chose packed array. Thank you and sorry for my late reply.

Hi May I confirm if there is a typo on this example typedef bit [4:0] bsix; // multiple packed dimensions with typedef bsix [9:0] v5; // equivalent to bit[4:0][9:0] v5

typedef bsix mem_type [0:3]; // array of four unpacked ‘bsix’ elements mem_type ba [0:7]; // array of eight unpacked ‘mem_type’ elements // equivalent to bit[4:0][9:0] ba [0:3][0:7]

Should the last comment be bit[4:0] ba [0:3][0:7] instead of bit[4:0][9:0] ba [0:3][0:7]?

Yes you’re right! Thanks for catching it!

Got it, thanks. By the way, if I have a 3D array, and I want to be able to slice of a 2D portion when accessing it, would you recommend to build a 3D array as “logic [HEIGHT-1:0][WIDTH-1:0] array [DEPTH]” or “logic [WIDTH-1:0] array [DEPTH][HEIGHT]”

For example, I have several submodules that expect a 2D array input, and I plan to connect them by slicing off the 3D array, so just wondering which way is preferred, “logic [HEIGHT-1:0][WIDTH-1:0] array [DEPTH]” or “logic [WIDTH-1:0] array [DEPTH][HEIGHT]”

You can slice a 2D array out of a 3D array with both ways of coding, or even “logic array [width][depth][height]”. The difference is whether you want the 2nd (middle) dimension to be packed (left of array name) or unpacked (right of array name). In your example, since each “element” is only a single bit (logic), it probably doesn’t matter which way you code it; I would actually probably code it as “logic array [width][depth][height]” to clearly show each element is only a single bit. But if you really meant a 2D array of multi-bit vector, then I would use “logic [vector_width-1:0] array [depth][height]” to show that more clearly.

The packed vs unpacked dimensions matter more if you are instead creating multi-dimensional arrays of structs or more complex data types, in which case there may be rules that the data structures must be packed (on the left) for synthesis.

Got it, thanks for sharing 🙂

1- Why do we still need to use [7:0]? We can use `busB = busA[0+:8];` and use directly the number of bits. It avoids using paraneter like `bus[PARAM-1:0]`, better to write `bus[0+=PARAM]`

2- You said `bus[6+:2]` is equivalent to `bus[7:6]` how to use big endianness to get bus[6:7]? I guess it’s not possible.

Sorry, I misread and I simulated. We can’t define logic using +:, you can delete the question.

Hi, I am writing a code in system verilog, and I wondered if there is a way to index an array from 1? Is this correct, and can I access array a from 1 to q_size?

logic a [1:q_size];

Also, unrelated question but I would be glad if you could give me an answer: I generate a queue made of number (q_size) of my blocks, which are connected with signals, so I need a number (q_size) of signals, which I intenteded to define as example above. In generate for loop I map signals to ports this way:

my_module( .my_input(a[i+1]) //i is genvar )

Is this correct, can I work with indexes this way? Thank you VERY MUCH 🙂

Hi Ivana. It is certainly possible to index an array from 1, like what you wrote. Hardware designers generally like to think and code with index starting with 0 for convenience (for example in your code you wouldn’t need a +1 if the index started at 0). Yes you can use a genvar to index into a vector. Your code should work.

Thanks for the awesome blog posts. Arrays with negative indices seem to compile (at least using the Cadence tools). What I am wondering is, do arrays with negative indices actually synthesize?

parameter integer unsigned width = 0; logic [width-1:0] x;

This compile and in SimVision I actually see x[-1:0] in waves. I am curious to know if this is a quirk in the simulator or does this actually synthesize to a two bit logic equivalent?

Thanks, Sami

Hi Sami. Another interesting question 🙂 I have never used a negative index because that goes against the coding guidelines at work, so I don’t know for sure… but I would guess it would work as expected (if your synthesis tool doesn’t complain).

I have a question about the comparison of mixed arrays that I think would fit in here:

consider the following code:

module testModule #( parameter logic [7:0] TP_A = 8’h01, parameter logic [7:0] TP_B = 8’h02, parameter logic [7:0] TP_C = 8’h03, parameter logic [7:0] TP_D = 8’h04 )( input logic clock_104, input logic reset_n, input logic [7:0] sampleData [12:0] output logic [7:0] errorCnt );

logic [7:0] comp0 [12:0]; assign comp0 = ‘{TP_A,TP_B,TP_C,TP_D,TP_A,TP_B,TP_C,TP_D,TP_A,TP_B,TP_A,TP_B,TP_C};

always @(posedge clock_104) begin if (reset_n == 1’b0) errorCnt <= '{default:0}; else begin if (sampleData == {TP_A,TP_B,TP_C,TP_D,TP_A,TP_B,TP_C,TP_D,TP_A,TP_B,TP_A,TP_B,TP_C} ) begin // this generates an error of illegal comparison to unpacked array if (sampleData == comp0 ) begin // this works fine

Why does one if statement work fine and the other one creates an error? Are they not doing the same thing?

Thank you for your help!

Hi Tom. I tried some variations of your experiment.

A pure array literal. This worked. if (sampleData == ‘{8’h00, 8’h00, 8’h00, 8’h00, 8’h00, 8’h00, 8’h00, 8’h00, 8’h00, 8’h00, 8’h00, 8’h00, 8’h00}

Add an apostrophe in front of the array: if (sampleData == ‘{TP_A,TP_B,TP_C,TP_D,TP_A,TP_B,TP_C,TP_D,TP_A,TP_B,TP_A,TP_B,TP_C} )

The simulator (VCS 2014.10) then reported the following error:

Error-[SV-IUAP] Illegal use of assignment pattern design.sv, 22 “(sampleData == ‘{TP_A, TP_B, TP_C, TP_D, TP_A, TP_B, TP_C, TP_D, TP_A, TP_B, TP_A, TP_B, TP_C})” An assignment pattern can only be used in one of the sides of an assignment-like context. Please consider rewriting it using individual array elements.

I suspect the simulator is somehow trying to do two levels of assignments in the error case, and that cannot be done within a comparison? However, I couldn’t find a statement in the LRM that explained why it is not allowed either…

That is a kind of weird. Thank you for taking the time and looking into this. I appreciate it.

is input node [6-1:0] A the same same input node [5:0] A

Hi Mike. Yes that is identical.

Hi Jason, Thank you for the wonderful forum. I have a few queries. How can I check the bit order ( MSB first and LSB last) of a packed array? e.g. input logic[7:0] test1; and output logic [7:0] out1; Would be kind to explain me.

There are several SystemVerilog system tasks that you can use to do that. See section 20.7 Array Querying Functions of the 2012 SystemVerilog LRM. Some examples are:

  • $left shall return the left bound of the dimension. For a packed dimension, this is the index of the most significant element. For a queue or dynamic array dimension, $left shall return 0.
  • $right shall return the right bound of the dimension. For a packed dimension, this is the index of the least significant element. For a queue or dynamic array dimension whose current size is zero, $right shall return –1.
  • For a fixed-size dimension, $increment shall return 1 if $left is greater than or equal to $right and –1 if $left is less than $right. For a queue or dynamic array dimension, $increment shall return –1.
  • $low shall return the same value as $left if $increment returns –1, and the same value as $right if $increment returns 1.
  • $high shall return the same value as $right if $increment returns –1, and the same value as $left if $increment returns 1.
  • $size shall return the number of elements in the dimension, which is equivalent to: $high – $low + 1.

Thank you Jason for your venerated inputs.

I’d like to try this, but not having much luck.. for example, I’ve created an .sv module that declares eight, 16-bit registers:

module test ( output reg [ 15 : 0 ] regTest[ 0 : 7 ] … );

Then in another .sv file, I try to instantiate like this:

wire [15:0]test[0:7]; test test_u0 ( .regTest (test) … );

However the above says an error that it cannot bind.. I’ve tried using the packed syntax, but it doesn’t seem to make any difference.. any suggestion what might be the problem?

Thanks! Ben

Hi Ben. I tried your code out on edaplayground here , and didn’t have any problem. Perhaps something else was causing the issue?

Hi want to extract only columns in packed 2-D array, for eg logic [255:0][299:0] array1 has 256 rows each having 300 bits ; if I wanted to extract 1st column through array slicing operation how do I do it? Like array1[0] gives first row array1[1] gives second row etc ; Thanks a lot

Hi Venkat. The array definition makes extracting one dimension easier than the other, so you should be careful about how you define the array. To accomplish what you want to do, you can write a loop to extract each element that you need and assign that element to a new 256-entry single dimensional array.

Can I include an unpacked array in a struct or an interface? For example, I like to pass an FIFO and some other info of a module to another to snooping. can I have a struct like this: typedef struct packed { logic [5:0] dev_sel; logic [31:0] wr_pending_fifo_dv; logic [31:0] wr_pending_fifo_mem [128]; } dev_wr_fifo_s;

Would an interface have the same elements?

Thanks Agnes

Hi Agnes. If you create an unpacked struct (typedef struct, without the packed keyword), then you can have an unpacked array like the wr_pending_fifo_mem in the structure. However, Design Compiler will not synthesize an unpacked struct. What are you trying to achieve? Putting a FIFO into a struct seems to be a bit of a strange construct.

Always thanks to your post. Again, I hope to ask clarify below comment. /////////////////////////////////////////////////////////////////////////// bit [3:0] [7:0] joe [0:9] // 10 elements of 4 8-bit bytes // (each element packed into 32 bits) typedef bit [4:0] bsix; // multiple packed dimensions with typedef bsix [9:0] v5; // equivalent to bit[4:0][9:0] v5 typedef bsix mem_type [0:3]; // array of four unpacked ‘bsix’ elements mem_type ba [0:7]; // array of eight unpacked ‘mem_type’ elements // equivalent to bit[4:0] ba [0:3][0:7] – thanks Dennis! /////////////////////////////////////////////////////////////////////////// Considering its semantic, I think it needs to be fixed as below. In my previous experience, I was also confused for that. 1. equivalent to bit[4:0][9:0] v5 => equivalent to bit[9:0][4:0] v5 2. equivalent to bit[4:0] ba [0:3][0:7] => equivalent to bit[4:0] ba [0:7][0:3]

Hi Yunsung. I just ran a test to prove it to myself. You’re right! Thanks for correcting this major mistake!

Is accessing to array slices with dynamic indexing but fixed width synthesizable? For example:

// input_byte is a 8 bit logic input // input_index is 3 bit logic input localparam int unsigned FIXED_WIDTH = 8; logic[63:0] data_array; data_array[input_index *FIXED_WIDTH +: FIXED_WIDTH] <= input_byte;

Hi Veli. I think that should be synthesizable. I have written similar code where the LHS is a dynamic index to an array. I have not additionally used a fixed width slice, but I think since the width is a fixed parameter, it shouldn’t be a problem. A dynamic index and a dynamic width, I think would be a problem.

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Introduction to Verilog Synthesis

Verilog is a popular hardware description language used for modeling and simulating digital systems. However, to turn a Verilog design into an actual hardware circuit, it needs to undergo synthesis. Verilog synthesis is the process of converting behavioral Verilog code into a gate-level representation that can be implemented on an FPGA or ASIC device. In this tutorial, we will explore the fundamentals of Verilog synthesis and the steps involved in the process.

Understanding Verilog Synthesis

The primary goal of Verilog synthesis is to convert the high-level behavioral description of a digital design into a gate-level netlist. This netlist comprises logic gates, flip-flops, and other elements that implement the desired functionality. The synthesis tool analyzes the Verilog code and optimizes it for area, power, and timing constraints to achieve the best possible hardware implementation.

Steps in Verilog Synthesis

The process of Verilog synthesis involves several key steps:

  • Design Compilation: The Verilog source code is compiled by the synthesis tool to create an abstract representation of the design.
  • Elaboration: The design hierarchy is expanded, and all instances are connected, forming a complete design database.
  • Synthesis: The design database is analyzed, and RTL (Register-Transfer Level) constructs are converted into gates and flip-flops.
  • Mapping: The synthesized RTL elements are mapped to technology-specific cells in the target device library.
  • Optimization: The tool performs various optimizations to minimize area and maximize performance.
  • Static Timing Analysis: The timing paths in the design are analyzed to ensure that they meet timing requirements.
  • Netlist Generation: Finally, the synthesis tool generates a gate-level netlist that represents the hardware implementation of the design.

Example: Verilog Synthesis

Let's consider a simple Verilog code snippet for a 2-to-1 multiplexer and understand how it goes through the synthesis process.

The above Verilog code describes the behavior of a 2-to-1 multiplexer. When sel is 0, the output y is equal to input a, and when sel is 1, the output y is equal to input b.

Common Mistakes in Verilog Synthesis

  • Using non-synthesizable constructs, such as blocking assignments in sequential logic.
  • Not considering timing constraints during the design phase, leading to timing violations in synthesis.
  • Using overly complex coding styles that hinder synthesis tool optimizations.
  • Not verifying the synthesized netlist against the original RTL code for functional equivalence.

Frequently Asked Questions (FAQs)

  • Q: Can I synthesize Verilog code for both FPGAs and ASICs? A: Yes, Verilog code can be synthesized for both FPGAs and ASICs, but some considerations may vary between the two targets.
  • Q: What are the main factors affecting synthesis results? A: The quality of synthesis results is influenced by design complexity, coding style, optimization settings, and target technology library.
  • Q: Is it possible to control the synthesis optimizations? A: Yes, most synthesis tools provide options to control various optimization levels, allowing designers to balance between area, power, and performance.
  • Q: How can I ensure my design meets timing requirements after synthesis? A: Performing static timing analysis (STA) after synthesis can help identify and resolve timing violations in the design.
  • Q: Are there any restrictions on the use of Verilog constructs for synthesis? A: Yes, certain Verilog constructs, like tasks, functions, and system tasks, may not be synthesizable and should be used only for testbenches and simulation.

Verilog synthesis is a crucial step in converting behavioral Verilog code into a hardware implementation. Understanding the synthesis process, avoiding common mistakes, and adhering to best practices ensure efficient and accurate hardware designs. By following proper design guidelines and utilizing synthesis tools effectively, designers can achieve optimal results in terms of area, power, and performance for their digital designs.

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Verilog Task

A function is meant to do some processing on the input and return a single value, whereas a task is more general and can calculate multiple result values and return them using output and inout type arguments. Tasks can contain simulation time consuming elements such as @ , posedge and others.

A task need not have a set of arguments in the port list, in which case it can be kept empty.

Static Task

If a task is static, then all its member variables will be shared across different invocations of the same task that has been launched to run concurrently

The task-enabling arguments (x, y, z) correspond to the arguments (a, b, c) defined by the task. Since a and b are inputs, values of x and y will be placed in a and b respectively. Because c is declared as an output and connected with z during invocation, the sum will automatically be passed to the variable z from c .

Automatic Task

The keyword automatic will make the task reentrant, otherwise it will be static by default. All items inside automatic tasks are allocated dynamically for each invocation and not shared between invocations of the same task running concurrently. Note that automatic task items cannot be accessed by hierarchical references.

For illustration, consider the static task display which is called from different initial blocks that run concurrently. In this case, the integer variable declared within the task is shared among all invocations of the task and hence thev displayed value should increment for each invocation.

If the task is made automatic, each invocation of the task is allocated a different space in simulation memory and behaves differently.

Global tasks

Tasks that are declared outside all modules are called global tasks as they have a global scope and can be called within any module.

If the task was declared within the module des , it would have to be called in reference to the module instance name.

Difference between function and task

Although Verilog functions and tasks serve similar purposes, there are a few notable differences between them.

When a function attempts to call a task or contain a time consuming statement, the compiler reports an error.

Disable Task

Tasks can be disabled using the disable keyword.

When display task was launched by the first initial block, T_DISPLAY started and got disabled when time reached 50 units. Immediately the next block S_DISPLAY started and ran to completion by 80 units.

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verilog task synthesizable

Is Function/Task synthesizable?

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1. Is function/task in Verilog synthesizable? or It works just in simulation. 2. If I call a function several times, what does it means? 2.1 I use a hardware several time 2.2 I duplicate hardware in Chip. 3. How can I use a hardware in a "time-sharing" fashion? (for Example: to save power or save area)

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When software types first dive into synthesis they often find they have a hard time meeting timing. That is because they are only thinking logically and not physically. Ultimately you are doing circuit design, and you need to know what circuit will be generated by the code you write. I like this book because it approaches HDL from a circuit design perspective instead of a language perspective. It give examples of most of the basic building block circuits you would want to use, and examples in both verilog and vhdl that will generate said circuit.

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Kevin Neilson

Timeslicing is a time-honored technique. An optimal design will usually use the least amount of gates, timesliced so they run at the fastest possible speed. Timeslicing usually must be coded explicitly and can't be done by calling functions at different times. -Kevin

> That is because they are only thinking logically and not physically

> Ultimately you are doing > circuit design, and you need to know what circuit will be generated by > the code you write.

> I like this book because it approaches HDL from a > circuit design perspective instead of a language perspective. It give > examples of most of the basic building block circuits you would want > to use, and examples in both verilog and vhdl that will generate said > circuit.

Thank you for your tip.

>(The same is usually true of > synthesizing 'for' loops: the index is spread across die space, not > time.) That is, calling a function twice will not use the same > hardware. (A lot of the function calls I use are 'constant' functions, > like log2, and get resolved presynthesis, using no hardware.)

> timeslicing is a time-honored technique. An optimal design will usually

> use the least amount of gates, timesliced so they run at the fastest > possible speed. Timeslicing usually must be coded explicitly and can't > be done by calling functions at different times.

Thank you for your insidely explanation. I got my most questions answered.

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Petter Gustad

> 1. Is function/task in Verilog synthesizable? or It works just in > simulation.

> 2. If I call a function several times, what does it means? > 2.1 I use a hardware several time > 2.2 I duplicate hardware in Chip.

> 3. How can I use a hardware in a "time-sharing" fashion? (for > Example: to save power or save area)

-- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?

>> (The same is usually true of >> synthesizing 'for' loops: the index is spread across die space, not >> time.) That is, calling a function twice will not use the same >> hardware. (A lot of the function calls I use are 'constant' functions, >> like log2, and get resolved presynthesis, using no hardware.) > what does "resoved presynthesis, using no hardware"? Do you means the > synthsizer calculates log2 > (0.30103) and code it in binary float number(0.01001)? >

> >> timeslicing is a time-honored technique. An optimal design will usually >> use the least amount of gates, timesliced so they run at the fastest >> possible speed. Timeslicing usually must be coded explicitly and can't >> be done by calling functions at different times. > There are any code example to show how to do it ?

I don't believe there is any code; it's just schematics. But as Ryan says, it's really more important to visualize the circuit than the code itself. If you can't visualize the hardware you are describing, you will have trouble writing code for it.

mk's profile photo

>humann < [email protected] > writes: > >> 1. Is function/task in Verilog synthesizable? or It works just in >> simulation. > >A function can be just a block of combinatorial logic and hence >synthesizable. A task is the same but with more than one output. >

>> 2. If I call a function several times, what does it means? >> 2.1 I use a hardware several time >> 2.2 I duplicate hardware in Chip. > >Mostly two (or more) instances of the same combinatorial block. > >> 3. How can I use a hardware in a "time-sharing" fashion? (for >> Example: to save power or save area) > >You can use resource sharing to share a piece of logic but it's very >dependant upon the synthesis tool how it is handled.

Or one can implement explicity resource sharing by controlling the inputs and outputs of the hardware. Say you have a design which needs to implement an algorithm needing several multiplications. Instead of using a separate multiplier (ie making a function call) for each multiplication, one can instantiate one multiplier and change its inputs over several cycles to different values and store the outputs to different locations. This requires implementation of a state machine which controls which values are muxed at the inputs and which the results go each cycle but it can be a huge area/power saver IF one can afford the latency it generates. There are always solutions in the middle, ie. instead of using one multiplier and getting a latency of N (assuming there were N multipliers in the original requirement) one can use 2 multipliers and reduce the latency to N/2 etc.

Dwayne Dilbeck's profile photo

Dwayne Dilbeck

"humann" < [email protected] > wrote in message news:[email protected]...

>Unfortunately I am not aware of an IEEE subset of verilog that is declared >synthesizable. VHDL does 1076.6. I believe there was a IEEE 1364.1 subset >that was being worked on a long time ago, but I don't know what happened to >it.

http://ieeexplore.ieee.org/servlet/opac?punumber=4140790

"mk" <kal*@dspia.*comdelete> wrote in message news:[email protected]...

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[SOLVED]   Is $signed() task is synthesizable in verilog 2001?

  • Thread starter gsdeshpande
  • Start date Apr 10, 2011
  • Apr 10, 2011

gsdeshpande

Newbie level 2.

Is $signed() /$unsigned() synthesizable in verilog?  

Member level 5

Hi, yes and it is even recommended for better QoR for Design Compiler. Synopsys even has a great appnote about this called "Coding Guidelines for Datapath Synthesis". You can find it on solvnet. Terry  

  • Apr 11, 2011

Advanced Member level 3

no, it doesn't support synthesis!  

sakshi gupta

Full member level 1.

Yes , it is synthesisable  

Thanks Terry. The document is really helpful.  

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Synthesizable and Non-Synthesizable Verilog constructs

verilog task synthesizable

11 comments:

verilog task synthesizable

and what about loops,are they synthesizable?????

If you understand what is verilog you will realize that loops make no sense and serve no purpose.

please explain me properly

for and do-while loops are synthesizable. The repeat is not synthesizable.

loops are synthesize-able until they don't depend on inputs. e.g you have loop for(int i = 0; i<10; i++) this is synthesize-able. but if you have loop for(int i = 0; i < inp1; i++) this is not synthesize-able.

They are synthesizable as long as they are running for a fixed number of times but not a dynamic value. Ex: for(i=0;i<5;i++) is fine but for(i=0;i<j;i++) is not.

Yes, for and while loops are synthesizable

wand, wor are synthesizable or not?

why user define primitive and timing is not synthesizable??

$size is synthesisable?

Why are they not synthesizable ?

Your Comments... (comments are moderated)

IMAGES

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COMMENTS

  1. Task

    Learn how to write tasks in Verilog that can be called repeatedly, have time delays, and be synthesized. See the difference between automatic and non-automatic tasks, and the rules and examples of tasks with inputs and outputs.

  2. Writing synthesizable task in verilog

    #1 S siddharthakala Member level 2 Joined Jul 20, 2010 Messages 53 Helped 6 Reputation 12 Reaction score 5 Trophy points 1,288 Location bangalore Activity points 1,732 Can we use tasks (or functions) in sequential always blocks in synthesizable verilog code??

  3. Task synthesis in verilog

    Task synthesis in verilog SystemVerilog PayalAshar January 29, 2019, 6:55am 1 If I am writing a "task" or a "function" in verilog and calling that "task" or "function" in the same module where I have written task then how will it be synthesized? How my hardware will look?

  4. Using Tasks and Functions in Verilog

    November 2, 2020 In this post we look at how we use tasks and functions in verilog. Collectively, these are known as subprograms and they allow us to write verilog code which is reusable. As with most programming languages, we should try to make as much of our verilog code as possible reusable.

  5. PDF Synthesizable System Verilog

    When the SystemVerilog standard was first devised, one of the primary goals was to enable creating synthesizable models of complex hardware designs more accurately and with fewer lines of code. That goal was achieved, and Synopsys has done a great job of implementing SystemVerilog in both Design Compiler (DC) and Synplify-Pro.

  6. PDF Synthesizing SystemVerilog

    Much of SystemVerilog is Intended to be Synthesizable SystemVerilog-2005/2009/2012 assertions test program blocks clocking domains mailboxes semaphores constrained random values classes inheritance strings dynamic arrays associative arrays queues 2-state types shortreal type globals process control

  7. system verilog

    system-verilog Share Follow edited Jan 7, 2023 at 11:30 toolic 59.4k 19 77 118 asked Jan 7, 2023 at 6:51 James Strieter 797 3 10 1 It is definitely possible as some tools used to support it. But most tools in use today have chosen not to support more advance behavioral synthesis and stick with RTL. - dave_59 Jan 7, 2023 at 17:33

  8. Synthesizability of tasks

    Synthesizability of tasks SystemVerilog farhad November 10, 2021, 9:50am 1 Hi Consider we want to model some communication protocol in an interface, using tasks. Such a task will probably contain sequential logic. My question is that is it possible to have a task with sequential logic, in a module/interface which is supposed to be synthesized?

  9. task in Verilog

    Type make to run the simulation. You should see several lines of output reporting a->q and b->w. Verify that the bits are correctly reversed in each case.

  10. Writing synthesizable Verilog

    A subset of Verilog is used for specifying synthesizable circuits. Verilog (which subsumed SystemVerilog as of the 2009 standardisation) is a unified language, serving distinct purposes of modern hardware design. These are: circuit design/specification at different levels of abstraction: structural/register-transfer level ( switch/transistor;

  11. PDF Verilog Synthesis

    Synthesis converts Verilog (or other HDL) descriptions to an implementation using technology-specific primitives: For FPGAs: LUTs, flip-flops, and RAM blocks For ASICs: standard cell gate and flip-flop libraries, and memory blocks 2 Why Perform Logic Synthesis? Automatically manages many details of the design process: Fewer bugs

  12. SystemVerilog Arrays, Flexible and Synthesizable

    Conclusion. This article described the two new types of SystemVerilog arrays— packed and unpacked —as well as the many new features that can be used to manipulate SystemVerilog arrays. The features described in this article are all synthesizable, so you can safely use them in SystemVerilog based RTL designs to simplify coding.

  13. Is task or automatic task synthesizable using verilog (not System

    Ayesha1 November 22, 2023, 6:19pm 1 Is task or automatic task synthesizable using verilog (not System Verilog)? dave_59 November 23, 2023, 2:01am 2 In reply to Ayesha1: It should be as long as all the statements inside the task (its body) are synthesizable as well.

  14. Introduction to Verilog Synthesis

    A: Yes, certain Verilog constructs, like tasks, functions, and system tasks, may not be synthesizable and should be used only for testbenches and simulation. Summary. Verilog synthesis is a crucial step in converting behavioral Verilog code into a hardware implementation.

  15. Verilog Task

    Verilog Task. A function is meant to do some processing on the input and return a single value, whereas a task is more general and can calculate multiple result values and return them using output and inout type arguments. Tasks can contain simulation time consuming elements such as @, posedge and others.

  16. Is Function/Task synthesizable?

    Is Function/Task synthesizable? 5,791 views humann Jan 3, 2008, 4:54:42 AM to The concept of "code reuse" in software is function. Every software guy knows that calling a function in C is 1....

  17. [SOLVED] Is $signed() task is synthesizable in verilog 2001?

    Activity points. 1,786. Hi, yes and it is even recommended for better QoR for Design Compiler. Synopsys even has a great appnote about this called "Coding Guidelines for Datapath Synthesis". You can find it on solvnet.

  18. hdl

    0. Anything you can execute in simulation could be synthesized if tools choose to support it. But most RTL synthesis tools do not support this. In your simple case, you could replace your event trigger with a task call (or void function call in SystemVerilog). always @ (posedge clk) begin count <= count + 1; x; end task x; flag <= 1; endtask.

  19. Synthesizable and Non-Synthesizable Verilog constructs

    Synthesizable and Non-Synthesizable Verilog constructs . ... 3'07, 32'd123, 8'hff), Signed constants (s) 3'bs101, module, endmodule, macromodule, ANSI-style module, task, and function port lists. system tasks, real constants ... They are synthesizable as long as they are running for a fixed number of times but not a dynamic value. Ex: for(i=0;i ...

  20. Synthesizable arithmetic shift in Verilog

    If it is not synthesizable, is there a different way to perform arithmetic shift on variables like a <= a>>>2 (this should give the quotient when a is divided by 4). verilog bit-shift